The present invention relates to a structure of an imaging device for a bonding apparatus and to an imaging method using the imaging device for a bonding apparatus.
The assembling of semiconductor devices includes: a die bonding step of bonding semiconductor chips cut out from a wafer on a lead frame or substrate; and a wire bonding step of wire-connecting pads on the semiconductor chips bonded on the lead frame or substrate to the lead frame or leads on the substrate. The wire bonding provides wire connections between the pads and leads by pressing a bonding tool such as a capillary with a wire inserted therethrough at a first bonding point on a lead or pad, thus bonding the wire with an ultrasonic vibration, and then looping the wire from the first bonding point toward a corresponding pad or lead, and pressing and bonding the wire at a second bonding point on the corresponding pad or lead with an ultrasonic vibration. Since wire bonding is required to provide precise connections between pads and leads that have small areas, it is necessary to press the leading end of a bonding tool such as a capillary precisely on the pads and leads.
However, the bonding accuracy between a lead frame or substrate and semiconductor chips is often varied, which can result in a deterioration in bonding quality unless the positional relationship is corrected.
To address this issue, it has been practiced that before wire bonding, pads and leads are imaged using a camera, the image is then processed to read a particular pattern as a binary image, and the positions of the pads and leads are detected and corrected accordingly.
However, if the difference in level between the surfaces of semiconductor chips and leads is increased with an increase in the size of the semiconductor device and the number of pins, the pads on the surfaces of the semiconductor chips and the lead frame or the leads on the surface of the substrate can not be included concurrently within the depth-of-field of the camera, resulting in defocusing either of the images to make position detection impossible.
For this reason, there has been a proposed method of providing two cameras that are focused, respectively, on chips and leads in the same field of view, imaging the chips and leads using the respective cameras, and performing position detection based on the images (see Patent Document 1, for example).
There has also been a proposed method of providing a shutter for switching optical paths in an optical system having two optical paths with different optical path lengths that include chips and leads within their respective depth-of-fields, and switching the optical paths by the shutter to image the chips and leads using a common camera through each optical path (see Patent Document 2, for example).
There has further been a proposed method of imaging semiconductor chips and leads at mutually different heights using three cameras (refer to Patent Document 3, for example).
[Patent Document 1] Japanese Patent Application Unexamined Publication Disclosure No. 2-301148
[Patent Document 2] Japanese Patent No. 3272640
[Patent Document 3] Japanese Patent Application Unexamined Publication Disclosure No. 5-332739
However, multilayer semiconductor devices in which semiconductor chips are stacked in multiple layers on a lead frame have started to be produced in the recent demand for capacity increase and space saving in semiconductor devices. Such stacking semiconductor chips in multiple layers increase the difference in level in the height direction of the semiconductor chips, requiring imaging devices available for the more increased difference in level in the height direction. In addition, the demand for space saving makes the pitch as well as the size of the pads on the semiconductor chips smaller. This requires an improved imaging accuracy to detect the positions of the pads accurately before wire bonding, requiring high-magnification imaging devices.
In contrast, the dimensional accuracy of lead frames is lower than that of semiconductor chips, and leads are often arranged in substantially varied positions. It is, therefore, necessary to image all the leads connected to the pads on the semiconductor chips to detect the positions of all the leads before wire bonding between each semiconductor chip and lead frame.
Trying to address such demands with the related arts disclosed in Patent Documents 1 to 3 requires multiple higher-magnification and small-field optical systems to be combined, where such higher-magnification optical systems would narrow the field of view imageable in each optical system. However, since the leads are provided around the semiconductor chips, the imaging area for detecting the positions of the leads becomes larger. Imaging such a large area using a small-field optical system for each semiconductor chip or each layer would take a long time to detect the positions of the leads, resulting in a problem that high-speed wire bonding cannot be achieved. On the contrary, combining multiple lower-magnification optical systems using the related arts disclosed in Patent Documents 1 to 3 would not take a long time to detect the positions of the leads, but the imaging accuracy for pads cannot be so high, resulting in a problem that the positions of pads arranged at a small pitch can not be detected accurately.
In other words, the demands for accurate imaging of semiconductor chips having a great difference in level in the height direction and the demands for reduction in time for imaging a lead frame to achieve high-speed wire bonding conflict with each other. The related arts disclosed in Patent Documents 1 to 3 cannot meet such conflicting demands.